1. Field of the Invention
The present invention relates generally to an oscillator biasing scheme in a phase-locked loop. More specifically, a supply independent oscillator biasing scheme for generating bias voltages and currents for an oscillator of a phase-locked loop is disclosed.
2. Description of Related Art
A phase-locked loop (PLL) generally comprises a phase detector, a low-pass loop filter, and a voltage-controlled oscillator (VCO). The VCO is an oscillator that produces a periodic wave form as an output signal, the frequency of which may be varied about some free-running frequency depending upon the value of the applied voltage. The free-running frequency is the frequency of the oscillator signal or the VCO output when the applied voltage is 0.
The phase detector receives an incoming signal and the output signal of the VCO and produces a phase detector output signal. The phase detector output signal represents the phase difference between the incoming and oscillator signals. The phase detector output signal is filtered through the low pass filter. The output of the low pass filter is the output of the PLL and the applied voltage to the VCO used to change the frequency of the VCO output. The closed-loop operation of the circuit maintains the VCO frequency locked to that of the incoming signal frequency.
If the applied signal of the VCO has the free-running frequency as an initial frequency, the PLL will acquire lock and the VCO will track the incoming signal frequency over some range, provided that the incoming signal frequency changes slowly. However, the loop will remain locked only over some finite range of frequency shift.
When the loop is operating in lock, the incoming signal and the VCO output signal fed to the phase comparator are of the same frequency. When the loop is trying to achieve lock, the output of the phase comparator contains frequency components at the sum and difference of the signals compared. The low-pass filter passes only the lower frequency component of the signals so that loop can obtain lock between incoming and VCO signals.
During lock, the output of the low-pass filter is the value needed to hold the VCO in lock with the incoming signal. The VCO then outputs a fixed amplitude wave signal at the frequency of the incoming signal. A fixed phase difference between the incoming and the VCO output signals to the phase comparator results in a fixed applied voltage to the VCO. Changes in the incoming signal frequency then results in change in the applied voltage to the VCO.
The limited operating range of the VCO and the feedback connection of the PLL circuit results in two frequency bands specified for a PLL: a capture range and a lock range. The capture range of the PLL is the frequency range centered about the VCO free-running frequency over which the loop can acquire lock with the input signal. The lock range of the PLL is generally wider than the capture range and is the range over which the PLL can maintain lock with the incoming signal once the PLL achieves capture. Within the capture-and-lock frequency ranges, the applied voltage drives the VCO frequency to match that of the incoming signal.
A PLL can be used in a wide variety of applications, including (1) modems, telemetry receivers and transmitters, tone decoders, AM detectors, and tracking filters; (2) demodulation of two data transmission or carrier frequencies in digital-data transmission used in frequency-shift keying (FSK) operation; (3) frequency synthesizers that provide multiples of a reference signal frequency (e.g. the carrier for the multiple channels of the citizen's band (CB) unit or marine-radio-band unit can be generated using a single-crystal-controlled frequency and its multiples generated using a PLL); and (4) FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage.
One example of a VCO implementation is a multiple-stage differential ring oscillator constructed using identical delay stages. Because each of the multiple stages are identical in construction, the delay of each stage is assumed to be the same. In such a differential ring design, the frequency of the VCO output signal is 1(2.times.number of stages.times.the delay of each stage). Thus, the frequency of the VCO output signal is 1/(8.times.the delay of each stage) for a four-stage differential ring oscillator.
The performance of the PLL is dependent in part upon the time required for the VCO to acquire lock. The acquisition time is in turn dependent upon the phase difference between the incoming and VCO output signals. Reducing the range of the initial phase error uncertainty in the VCO output signal thus reduces the acquisition time.
Each delay stage of the VCO generally includes various biasing currents and reference voltages. These biasing currents and reference voltages may be generated by a VCO biasing scheme or biasing block. Since the loop filter of the PLL controls the VCO frequency through the bias block, the bandwidth of the biasing scheme is preferably sufficiently wide to minimize any additional delay. Such additional delay would manifest as a higher order pole in the loop transfer function. The wide bandwidth also facilitates fast acquisition of the incoming signal. Further, to achieve low supply voltage operation, the delay cell current sources and sinks are generally implemented with metal-oxide semiconductor ("MOS") devices. To improve the high frequency power supply rejection of the VCO, the parasitic capacitances of these delay cell current source/sink MOS devices are typically minimized by constructing these MOS devices with short channel lengths.
However, providing short channel lengths reduces the output impedance of these delay cell current source/sink MOS devices. Such reduction in the output impedance degrades the immunity of the VCO to static power supply variations. In conventional PLL's and VCO's, a replica biasing scheme is sometimes utilized to overcome this potential trade-off. However, the replica biasing scheme typically does not possess the wide-bandwidth critical in fast acquisition of the incoming signal.
Thus, it is desirable to provide a VCO biasing scheme which ensures that the delay cell and thus the VCO frequency are immune to variations in the supply voltage. It is further desirable to provide a biasing scheme having a wide bandwidth.